@prefix p: <http://www.wikidata.org/prop/> .
@prefix rdfs: <http://www.w3.org/2000/01/rdf-schema#> .
@prefix schema1: <http://schema.org/> .
@prefix skos: <http://www.w3.org/2004/02/skos/core#> .
@prefix wd: <http://www.wikidata.org/entity/> .
@prefix wds: <http://www.wikidata.org/entity/statement/> .
@prefix wdt: <http://www.wikidata.org/prop/direct/> .
@prefix wdtn: <http://www.wikidata.org/prop/direct-normalized/> .
@prefix wikibase: <http://wikiba.se/ontology#> .
@prefix xsd: <http://www.w3.org/2001/XMLSchema#> .

wd:Q17637401 rdfs:label "ريسك-فايف"@ar,
        "RISC-V"@ast,
        "RISC-V"@ca,
        "RISC-V"@cs,
        "RISC-V"@de,
        "RISC-V"@de-ch,
        "RISC-V"@el,
        "RISC-V"@en,
        "RISC-V"@en-ca,
        "RISC-V"@en-gb,
        "RISC-V"@eo,
        "RISC-V"@es,
        "RISC-V"@et,
        "RISC-V"@eu,
        "ریسک پنج"@fa,
        "RISC-V"@fi,
        "RISC-V"@fr,
        "RISC-V"@ga,
        "RISC-V"@he,
        "RISC-V"@hu,
        "RISC-V"@it,
        "RISC-V"@ja,
        "RISC-V"@ko,
        "RISC-V"@mn,
        "RISC-V"@mul,
        "RISC-V"@nb,
        "RISC-V"@nl,
        "RISC-V"@pl,
        "RISC-V"@pt,
        "RISC-V"@pt-br,
        "RISC-V"@qu,
        "RISC-V"@ro,
        "RISC-V"@ru,
        "RISC-V"@sl,
        "RISC-V"@sr,
        "RISC-V"@sv,
        "RISC-V"@tr,
        "RISC-V"@uk,
        "RISC-V"@vec,
        "RISC-V"@vi,
        "RISC-V"@wuu,
        "RISC-V"@yue,
        "RISC-V"@zh ;
    schema1:dateModified "2026-08-26T12:12:49+00:00"^^xsd:dateTime ;
    schema1:description "conjunt d'instruccions RISC de codi obert"@ca,
        "otevřena instrukční sada a architektura procesoru"@cs,
        "offene Befehlssatzarchitektur"@de,
        "open-source CPU hardware instruction set architecture"@en,
        "malfermitfonta instrukciara arkitekturo"@eo,
        "Arquitectura de CPU basada en el Conjunto de Instrucciones Reducido cuya licencia es de código abierto"@es,
        "مجموعه دستور العمل متن باز برای پردازنده کامپیوتر"@fa,
        "suoritinarkkitehtuuri"@fi,
        "architecture et jeu d'instruction pour microprocesseur open source"@fr,
        "סט פקודות למעבד בקוד פתוח"@he,
        "standard aperto di un insieme di istruzioni per CPU"@it,
        "オープンソースのCPU命令セットアーキテクチャ"@ja,
        "opensource instructiesetarchitectuur"@nl,
        "arhitectură și set de instrucțiuni hardware cu sursă deschisă pentru microprocesoare"@ro,
        "Открытая процессорная микроархитектура"@ru,
        "typ av öppen processorarkitektur"@sv,
        "开源指令集架构"@zh ;
    schema1:version 2536660451 ;
    wikibase:identifiers 14 ;
    wikibase:sitelinks 32 ;
    wikibase:statements 49 ;
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        "RISCV"@en,
        "RISC V"@fa,
        "RISCV"@fa,
        "ریسک فایو"@fa,
        "ریسک وی"@fa ;
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