RISC-V

<http://www.wikidata.org/entity/Q17637401>

open-source CPU hardware instruction set architecture

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skos:altLabel	"RISC V"@en "RISC V"@fa "RISCV"@en "RISCV"@fa "ریسک فایو"@fa "ریسک وی"@fa
schema:description	"Arquitectura de CPU basada en el Conjunto de Instrucciones Reducido cuya licencia es de código abierto"@es "architecture et jeu d'instruction pour microprocesseur open source"@fr "arhitectură și set de instrucțiuni hardware cu sursă deschisă pentru microprocesoare"@ro "conjunt d'instruccions RISC de codi obert"@ca "malfermitfonta instrukciara arkitekturo"@eo "offene Befehlssatzarchitektur"@de "open-source CPU hardware instruction set architecture"@en "opensource instructiesetarchitectuur"@nl "otevřena instrukční sada a architektura procesoru"@cs "standard aperto di un insieme di istruzioni per CPU"@it "suoritinarkkitehtuuri"@fi "typ av öppen processorarkitektur"@sv "Открытая процессорная микроархитектура"@ru "סט פקודות למעבד בקוד פתוח"@he "مجموعه دستور العمل متن باز برای پردازنده کامپیوتر"@fa "オープンソースのCPU命令セットアーキテクチャ"@ja "开源指令集架构"@zh
schema:dateModified	"2026-08-26T12:12:49+00:00"^^xsd:dateTime
schema:version	2536660451
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